At BBWF 2016, Ethernity Networks will show how to open a network to new business with its leading SoC fully programmable solutions. Visit Stand G10

The increase of at least 50% performance at the flow processor pipeline is the next goal. The code synthesis passed on the new Xilinx devices

Single Chip G.fast Scalable DPU Architecture by Ethernity Networks Tested for 16, 24 and 48 Port Platforms

Distributed 5G Cloud-RAN architecture described in the document of 5G-PPP