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ENET4800: 40Gbps Access Flow Processor

ENET4800

40Gbps Fabric Flow Processor iBased on 40nm FPGA with a firm roadmap for 100Gbps based on 28nm FPGA

40Gbps deterministic throughput

36 Integrated SERDES
Integrated Packet Generator and analyzer to support wirespeed OAM/CFM functions
Supports 64K flows, 64K policers, 64K shapers, 64k queues and 8k logical ports enable full Ethernet switching between all 8k logical ports including SMTP, RSTP

Classify streams based on four configurable fields with four hierarchies

Full compliance to TR-101, TR-156, MEF standards including compliance with MEF 9 and MEF 14, 802.1ad, 802.1ah, 802.1ag, Y.1731, E-LAN, E-Line, including PBB-TE and T- MPLS together with full PBB implementing B and I Switch on a single device

Huge search engine data base through a single DDR, supporting up 1M entries for L2&L3, multicast, classification tables and 32 configurable search tables

Up to 64,000 buffers

Wire Speed Multicast

MEF compliance policing per flow with 64Kbps granularity and up to 64K streams.

Interfaces: 4 x XAUI, 24 x SGMII, and SPI-4

Hierarchical QoS with 3-5 hierarchies supporting WFQ, shaping, WRED and up to 64K queues

Management is performed through , generic Motorola CPU interface, MII , or optional integrated CPU .

Quality of Service (QoS) support, Including 4-8 priority queues per logical queue.



Description:

The ENET4800 40Gbps Access Flow Processor is a family of high performance configurable flow processor and traffic manager solutions optimized for the Metro Access Market.

The ENET4800 is a Fabric Flow Processors (FFP) integrating packet processing, protocol interworking, traffic management, and a Layer 2/3/4 switch.

Ethernity’s ENET4800 Fabric Processor family is optimized for the Carrier Ethernet Metro market. Compliant with the latest ITU-T and Metro Ethernet Forum specifications the ENET4800 is uniquely positioned to deliver an optimal solution for Ethernet Aggregators, PON OLTs, Mobile backhaul, edge and core Carrier Ethernet Switch and Router (CESR).

The ENET4800 FFP design is based on an extremely efficient architecture resulting in 80% die size reduction, and enabling an extremely cost effective implementation based on low cost FPGAs. The Ethernity ENET4800 solution retains the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with an ASIC solution.

 

Detailed Features:

Classification

  • Identifies flow and assign several flow IDs per stream, based on 6 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the  first 128 bytes of each frame
  • Assigns packet priority based on Ingress priority mapping configuration.
  • Up to 32K flows filter  for any classified packet based on the set of rules and set of the six

           programmable fields that assigns the ingress and egress flow ID

  • Rate dependent filters (e.g., limit rate of ingress IGMPv3 packets)
  • Configurable control of MAC address learning per port/VLAN
  • Configurable packet type rate limitation, e.g., rate of IGMPv3 and OAM packets

Forwarding and Switching

  • Fully IEEE 802.1Q compliant Ethernet switch with up to 16K Ethernet MACs, and 16K Active Network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS, or other packet fields programmed by the software and up to 4K Multicast groups.
  • 32 software programmable / configurable search tables
  • Configurable forwarding key per flow
  • Force association of specific MAC to a certain logical port and service.
  • 16K L3 address for supporting L3 forwarding
  • Partitioning of MAC address per VPN
  • L2 Control packets classifier for both user and Network L2 control protocol packets
  • Flexible forward decision per port per protocol with the ability to forward transparently, to  CPU or Discard
  • OAM packets classifier for both user and Network L2 control protocol packets
  • Support include ARP, DHCP, IGMPv2, IGMPv3 and other based on flexible configuration options

Quality of Service (QoS)

  • Hierarchical QoS with 3-5 hierarchies
  • Four priority queues per queue cluster
  • Priority Assignment per Port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS
  • Configurable L3/L2 Priority profiles per port
  • Ingress and Egress priority mapping per flow

 

Traffic Management

  • Support of Jumbo frames up to 16KB
  • Congestion manager: per queue, 8-profile WRED congestion avoidance with 8 programmable profiles
  • Hierarchical MEF 10 Metering – on port/service/flow level  - any combination of them can be mapped to a specific meter
    • 64K meters, with Granularity of 64Kbps
  • Re-marking – based on L3 or L2 information decoded from the packet or set by the service or the flow or the filter
    • Color marking can be done on 3 packet header hierarchies
    • Packet color can be mapped from any header/field decoded from the packet or set by the service/flow/filter
  • Scheduler: hierarchical, three level scheduler per MEF10
    • Port – WRR
      • Up to 256 ports per interface
    • logical port (cluster) - WFQ, WRR, Strict Priority
      • Up to 8K logical queues
    • Priority queue - WFQ, WRR, Strict Priority
      • 8 Priority queues per logical port/ queue
  • Queue manager
    • Virtual Output Queues architecture
    • Total of 64K Queues
    • Unlimited MC Burst support
    • Configurable Buffer size
  • Shaper per queue and each hierarchy – packet, cell or byte level
  • Performance monitoring counters for billing and diagnostics  - forward/drop packet and bytes green/yellow/red
  • Configurable MTU per priority queues or per cluster

Packet Editing

  • Extract, append, or swap in the egress any type of Layer 2/3 headers programmed by software, including MAC-in-MAC, Q-In-Q, MPLS, PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP or any other headers, controlled and configured by software.
  • Stamp data at the bit/byte level anywhere within the first 128 bytes including priority

           remapping, bytes count and DSCP.

  • L2 and L3 loop backs including swap of MAC SA and DA, Swap of IP

OAM

  • Hardware support for CFM compliant with 802.1ag
  • Support for four ME levels in compliance with TR-101 and TR-156
  • Rate limitation and filtering of OAM messages to prevent network attacks
  • L2/L3/L4 control packets classifier for both user and network L2 control protocol packets per flow
  • OAM packets classifier for both user and network L2 control protocol packets support include ARP, DHCP, IGMPv2, IGMPv3 and other based on flexible configuration options
  • Integrated packet generator and analyzer to support OAM packet generation and analysis per Y.1731, including per flow BERT
  • Hardware processing for L2, L3 Loop backs (swap L2 SA/DA, swap L3 SA/DA)
  • Hardware Fast protecting switching within micro seconds

L2 control protocols

  • L2 Control packets classifier for both user and Network L2 control protocol packets
  • Flexible forward decision per port per Protocol with the ability to forward transparently, to CPU or Discard
  • OAM packets classifier for both user and Network L2 control protocol packets
  • Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or Discard.

 

Security

  • L2 and L3 spoofing protection - SA/DA filtering per port/VLAN
  • Rate limitation on control packets, e.g., PPPoE, IGMPv3, OAM

IGMP Proxy

  • IGMP V2 and V3 compliance
  • IGMP packet snooping to processor in the U/S direction
  • Forwarding and multicast classification based on Source IP and Destination IP  

 

DDR2/3 SDRAM Interface

  • External 64/32-bit DDR2-SDRAM 133/166 MHz interface for deep packet buffering
  • Supports 128/256/512Mbit 8/16/32 bit width standard PC DDR SDRAM components

 

Host CPU Interface - Option

  • Motorola PowerPC 1&2 Glueless interface
  • Up to 66Mhz with 8/16/32 bit bus width
  • MII/GMII interface

 

Data Interfaces

  • Flexible up to 40GBbps

 

Reference Design Kit


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