One of the primary challenges facing access equipment designers is to minimize operational costs while simultaneously offering new services and maintaining revenue and gross margins. The growth of multimedia services (voice over Internet protocol (VoIP), video on demand (VOD)) and the move to Internet protocol television (IPTV) by the Regional Bell Operating Companies and other telcos means more application servers will be deployed closer to the access network. This implies the need for quality of service (QoS), traffic engineering, provisioning, and management. These requirements make the contribution of programmable packet processors increasingly important if not mandatory for next-generation access equipment line card designs.

Increasing bandwidth requirement results with the design of Next Generation Access Node based on 10G dual star architecture that requires dual 10G link towards the backplane. The dollar per port price Telco’s will pay for DSL cards has fallen precipitously in recent years, and is not going to change when migrating to ultra high-speed Next Generation Access Platforms.  In the face of falling prices, the challenge is to maintain same Access Node platform that can serve low end ADSL cards together with high-end PONs or High-end GbE access line cards

The ENET3xxx access flow processor (AFP) is the first device in the industry implemented on a low cost FPGA and combines the best aspects of programmable logic with the best aspects of interface customization and packet processor on a single chip. This combination is designed to deliver optimized product differentiation, Maximum flexibility, field upgradeability and lowest power consumption.

Figure 1 shows the ENET3xxx access flow processor for DSL Line card with connectivity to new 10G backplanes.

Figure 1. DSL Line card with 10G interface

The solution depicted in Figure 1 enables the support of as much as four Utopia/POS interfaces to support non blocking 3.2Gbps user traffic

Figure 2. VDSL Line card with 10G interface and G.999.1 channelized GbE interface

The solution depicted in Figure 2 supports up to six G.999.1 channelized GbE interfaces. Using a channelized GbE interface towards the DSP enables the support of more VDSL lines at a smaller package using a standard GbE interface, and thus support a non blocking VDSL line card solution with as many as 48 VDSL2 ports

ENET VDSL G.999.1 solution presentation

The ENET3000 AFP targets access equipment. The ENET3xxx performs advanced header parsing, pattern matching, bit manipulation, classification, packet modification, data movement, Inverse multiplexing, EFM bonding and extensive traffic management. It complies with all Carrier Ethernet requirements including TR-101, TR-156, and MEF.

Solution Overview

Ethernity Networks created a new class of low-cost, high-performance flow processor/traffic manager solutions optimized for metro access applications. Ethernity Network's ENET3xxx Access Flow ProcessorTM uses low cost FPGA as its vehicle platform and includes a field-proven, wire-speed pipeline architecture supporting up to 12Gbps throughput, where same code used on a more expensive FPGA supports up to 40Gbps.

The platform includes L2/L3/L4 switching, NAT/PAT, ATM SAR, EFM Bonding, programmable L2 to L5 classification, header processing supporting any type of protocol header, and comprehensive traffic management. The traffic management function includes MEF policing, Hierarchical QoS, Hierarchical Shaping and scheduling and traffic shaping per port/logical port/ priority.

The ENET3xxx interworking protocol includes software support for packet editing, which provides the ability to receive packets in any format and change the protocol per virtual output port to any other protocol, hence supporting GFP, Ethernet II, SNAP, Q-in-Q, MAC-in-MAC, MPLS, PPP, PPPoE, PPPoA, HDLC, L2TP, AAL5, EFM Bonding or any type of L2 protocol.

Table 1 shows the ENET3000 Access Flow Processor family.

Features & Benefits

The ENET3xxx FPGA-based AFPs enable the Programmable NetworksTM is customized, highly-configurable packet processors targeted for access applications. These devices adapt to the continuing evolution of protocols, as new features and capabilities are added after standards are ratified.

• Deterministic 12Gbps Metro Ethernet Packet Processor provides programmable protocol termination, ATM to IP Interworking, built-in hardware accelerators that accelerate traffic management, Search functions, filtering, Editing, manage EVC QoS, and maintain Service Level Agreements (SLAs).
• The only and First NPU and Traffic manager solution on lowest cost Pin Compatible FPGA devices offer a low-cost, small footprint, low power, FPGA-based packet processor solution for IP DSLAM, FTTx, MSAN, and other access equipment line cards.
• Integrated search engine using a single DDR2 Memory that search up to 128K entries
• System-Level Internetworking with Software API
• Fragment frames L2/L3/L4 switch
• Inverse Multiplexing
• Standard Ethernet Fragmentation - G.999.1
• Integrated double data rate (DDR) memory controllers provide packet buffering and QoS queuing for managing multiple traffic classes of voice, video, and data traffic.
• Dual integrated Gigabit Ethernet MACs with SGMII, GMII full-duplex, system-side interfaces reduce system footprint and simplify layout and backplane interface design.
• Integrated UTOPIA L2/POS-PHY L2 line-side interfaces to support various dual mode xDSL, PON, TDM framers, and analog front-end chip sets.
• Low Power
• Flexibility, Configurability & Field Upgradeability
• Superior Price/Performance