ENET3875 / G.999.1​


ENET3875ENET3875 is a DSL line card controller integrated on a single Xilinx ‘s Spartan6 FPGA that comes with six G.999.1 ports and two 2.5GbE ports to support Carrier Ethernet switching, hierarchical scheduling, OAM/CFM, G.999.1 channelized Ethernet and interworking with all available G.vector DSL DSPs. ENET3875 supports 8 EFM bonding groups span over, 48 DSL virtual ports, and can scale to support 256 virtual ports with 32 EFM bonding groups, using ENET4200 solution. A scale down version ENET 3825 provides extremely low cost offering for G.fast FTTdp terminals.


  • 8 Gbps fabric flow processor supports Carrier Ethernet switching,  hierarchical queuing and  scheduling, CFM/OAM through internal OAM processor offload, and protocol interworking, all integrated on a single  40 nm FPGA Xilinx ‘s Spartan6 FPGA
  • Eight integrated SERDES
  • Data Interfaces: QXAUI, SGMII, 6 x G.999.1 RGMII,  and MII.
  • Supports 2K flows, 2K policers, 2K shapers, 2K queues and 256 logical ports enable full Ethernet switching between all 256 logical ports
  • Full compliance to TR-101, MEF standards including compliance with MEF-9 and MEF-14, 802.1ad, 802.1ah, 802.1ag, Y.1731, E-LAN, E-Line
  • Deterministic 8Gbps throughput
  • Integrated OAM hardware processor with programmable packet generator and analyzer
  • EFM bonding supporting 8 EFM bonding groups, configurable to 2, 4, or 8 ports per group
  • Huge parameter search engine data base on a single DDR2, supporting up 128,000 entries including 128,000 MAC addresses or IP for L2 and L3 switching and routing, multicast, classification tables and 32 programmable search tables
  • Hierarchical QoS including WFQ,WRR, WRED and strict priority supporting up to 2K queues
  • MEF-10 compliance policing per stream with 64Kbps granularity
  • Advanced hierarchical classification and filtering, including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/ Swap/ Extract/ stamp in any preconfigured location in the first 128 bytes
  • Management is performed through generic CPU interface, MII, GMII or integrated CPU


ENET3875/G.999 access flow processor is a virtual ASSP SoC on FPGA, serving high throughput DSL line cards.

ENET3875/G.999 is a part of ENET38xx family of multiservice fabric flow processors (FFP), integrating packet processing, protocol interworking, traffic management, G.999.1, Ethernet and Layer 2/3/4 switch. The family also includes a high- end version ENET4200 to support two 10GE ports and 16 G.999.1 interfaces, serving 256 DSL modems on a single chip, and a low-end version ENET3825 with a single GbE interface to the network and a single G.999.1 i/o interface towards modems, supporting 16 modem units.

The design of ENET38xx is based on a specially efficient architecture resulting in 80%  size reduction, enabling an extremely cost-effective implementation based on low cost FPGAs. Ethernity’s ENET38xx retain the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASICs. ENET38xx are based on atomic level pipeline architecture, and support performance of up to 8Gbps on ultra low cost FPGA, with software configurable L2 to L4 protocol interworking, hierarchical multi field classification and flow identification, virtual Ethernet switch used for VPLS, E-LAN, E-TREE and E-Line, hierarchical policing, performance monitoring, packet editing, hierarchical scheduling and shaping.

Protocol interworking in ENET3875 includes software support for packet editing, which provides ability to receive packets in any format and change a protocol per virtual output port to any other protocol, hence it supports Ethernet II, SNAP, Q-in-Q, PPP, PPPoE, PPPoA, HDLC, L2TP, and AAL5.

Detailed Features

  • Identifies flow and assign several flow IDs per stream, based on 36 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the first 128 bytes of each frame
  • Assigns packet priority based on ingress priority mapping configuration
  • Up to 32K flows filter for any classified packet based on a set of rules and set of 64 configurable fields
Switching and Routing
  • Fully IEEE 802.1Q compliant Ethernet switch with up to 128K Ethernet MACs, and 16K active network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS or other packet fields programmed by the software and up to 4K multicast groups.
  • Configuration forwarding/switching decision per flow including connection oriented, L2, L3 or L4 forwarding decision
  • 32 software programmable / configurable search tables
  • Configurable forwarding key and learning key per flow
  • Force association of specific MAC to a certain logical port and service
  • 16K L3 address for supporting L3 forwarding
  • Partitioning of MAC address per VPNL2
  • Control packets classifier for both user and Network L2 control protocol packets
  • Flexible forward decision per port per protocol with the ability to forward transparently, to CPU or discard
  • Support includes ARP, DHCP, IGMPv2, IGMPv3 and other based on flexible configuration options
Quality of Service (QoS)
  • Eight priority queues per  virtual port ( virtual modem port)
  • Priority assignment per port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS
  • Configurable L3/L2 priority profiles per port
  • Ingress and egress priority mapping per flow
Policing and Shaping
  • Extended metering according to three color scheme as defined by MEF- 10, including color aware and coupling flag modes configured per flow
  • Supports up to 2K flows
  • Each ingress and egress flow can be configured in a granularity of 64Kbps up to 100Mbps
Traffic Management
  • Supports Jumbo frames up to 9.6KB
  • Supports eight priority queues per port / virtual port
  • Hierarchical scheduling
  • Programmable values for drop level
  • Two Weighted Fair queuing hierarchies
  • TCP friendly algorithm
Packet Editing
  • Extract, append, or swap in the egress any type of Layer 2/3/4 headers programmed by software, including
    Q-In-Q,  PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP,L3,  or any other header up to 128 bytes, controlled and configured by software
  • L2 and L3 loopbacks including swap of MAC SA and DA, swap of IP
  • Stamp data at the bit/byte level anywhere within the first 128 bytes including priority remapping, bytes count, sequence ID and DSCP
Traffic Monitoring
  • L2/L3/L4 control packets classifier for both user and network L2 control protocol packets per flow
  • Flexible forward decision per port/flow per protocol with the ability to forward transparently, to CPU or discard
  • OAM packets classifier for both user and network including support for 802.1ag
  • Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or discard
  • Integrated packet generator and analyzer to provide generation and analyzing of OAM packets and full support for Y.1731
IGMP Proxy
  • IGMP V2 and V3 compliance
  • IGMP packet snooping to processor in the U/S direction
  • Forwarding and multicast classification based on Source IP and Destination IP
EFM Bonding & Fragmentation
  • Supports 6 to 16 G.999.1 channelized Ethernet ports
  • Supports 8  EFM bonding groups according to 802.1ah
DDR SDRAM Interface
  • External 16-bit DDR2-SDRAM 400 MHz interface
  • Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components
Host CPU Interface
  •  Optional Motorola PowerPC 1&2 Glueless interface
  • Up to 66Mhz with 8/16/32 bit bus width
  • MII interface
  • 2 x 2.5G SGMII
  • 6 x G.999.1 GbE i/o supporting 48 VDSL ports
  • MII
  • CPU
  • 2 x 10GE XFI
  • 16 x G.999.1 GbE i/o supporting 256 VDSL modems
  • GMII
  • CPU
  • 1 x 2.5G SGMII
  • 1 x G.999.1 GbE i/o supporting 16 G. fast ports