ENET38xx PW - Pseudowire Ethernet​

Overview

ENET38xx – PW flow processor series combine Pseudowire Ethernet with Carrier Ethernet switch integrated on a single Xilinx ‘s Spartan 6 FPGA. ENET38xx -PW are uniquely positioned to deliver an optimal solution for Pseudowire gateways, TDM and Ethernet Access Devices (EAD), Carrier Ethernet microwave and cellular base stations. ENET38xx-PW come in two versions, one to provide 32 E1s/T1s through PMC interface, and the other to provide 4 x Ch STM-1/OC-3 supporting up to 336 DS1 channels.


Features

  • Combined switch and Pseudowire support on Xilinx’s Spartan 6 FPGA
  • Flexible support of interfaces that can be customized to any port / interface configuration
  • Universal gateway solution for legacy protocols
  • Sync Ethernet support
  • SAToP and CESoPSN with support for up to 336 PW channels
  • Hardware fast protecting switching within micro seconds
  • 1:1, N:1 and P2P network architecture

  • Clock recovery can be provided using third party IEEE 1588v2 clock recovery software application mapped to Ethernity hardware, or external clock recovery
  • Jitter buffer granularity of 125 micro sec (TDM frame)
  • Programmable packet editor supporting per flow multiple actions of Append/ Swap/ Extract/ stamp in any preconfigured location in the first 128 bytes
  • Management is performed through generic CPU interface, MII, GMII or integrated CPU

See Detailed Features

Description


Ethernity’s ENET38xx family of multiservice fabric access processors is optimized for mobile backhaul transmission networks and Carrier Ethernet Metro markets. Compliant with Metro Ethernet Forum specifications and IETF PWE3 RFC, ENET3800PW is uniquely positioned to deliver optimal solution for Pseudowire gateways, Carrier Ethernet Microwave and wireless base stations.

ENET3700PW-S is a pure Channelized SAToP implementation to support 4xSTM-1/OC-3 solution integrated on Spartan 6 150 FPGA with up to 336 PWE channels.

ENET3820PW-E is a pure SAToP implementation to support up to 64 E1/T1s integrated  on Spartan 6 75 FPGA with up to 64 PWE channels.

Detailed Features

Classification
  • Packet classification based on first 128 bytes in packet
  • Configurable functional actions: filtering, trapping, mirroring, packet editing (create/modify/delete), QoS remarking
  • Control filtering and forwarding
Pseudowire
  • Full support for: SAToP and CESoPSN supporting up to 336 channels
  • Adaptive Clock Recovery (1588v2), Common Clock, External Clock and Loopback timing modes
  • Supporting all PWE encapsulation options SAToP control word with and without RTP, including
    – 2xMPLS tags with/without VLAN
    – VLAN + 1 MPLS tag
    – MPLS over IP with/without VLAN
    – MPLS over UDP over IP with/without VLAN
  • Jitter and wander of recovered clocks conform to G.823/G.824, G.8261
  • Configurable jitter buffer size up to 256 msec
  • Jitter buffer granularity of 125 micro second
  • Configurable PW frame size
  • Option for E3/DS3
  • ATMoPW
Synchronization over Packet
  • 1588 end-to-end Transparent Clock 1588v2
  • Slave mode clock recovery through third part software
  • Synchronous Ethernet
DDR SDRAM Interface
  • External 16-bit DDR2-SDRAM 400 MHz interface
  • Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components
Host CPU Interface
  • Optional Motorola PowerPC 1&2 Glueless interface
  • Up to 66Mhz with 8/16/32 bit bus width
  • MII interface
 Interface Options
ENET3700PW
  • 4 x STM-1/OC-3 through SBI interface (336ch)
  • 2 x 100/1000 SGMII interfaces
  • 1 x DDR2s for packet buffer
  • 1 x MII for CPU
ENET3825PW
  • 64 E1/T1, DS3, 16 E1/T1, or 8 E1/T1s through PCM interface
  • 2 x 100/1000 MII interfaces
  • 1 x DDR2s for packet buffer
  • 1 x MII for CPU