ENET38xx - 10Gbps Carrier Ethernet Switch

Overview

product-explainedENET38xx is a family of high performance configurable fabric flow processors (FFP), implemented on Xilinx ‘s Spartan 6 FPGA, integrating packet processing, protocol interworking, hierarchical traffic management, CFM/OAM, MPLS-TP, and Layer 2/3/4 switch aimed for Metro Access Market. ENET38xx is specially optimized for Carrier Ethernet Access, AFDX, Metro Ethernet demarcation (NID) and service gateways. ENET38xx avaliable with different interfaces including QXAUI, SGMII, RGMII, 3SMII, and MII.


Features

  • 8 Gbps fabric flow processor supports  Carrier Ethernet switch,  hierarchical queuing and  scheduling, CFM/OAM through internal OAM processor offload, and protocol interworking, all integrated  on a single  40 nm FPGA Xilinx ‘s Spartan 6 FPGA
  • Eight integrated SERDES
  • Data interfaces: QXAUI, SGMII, RGMII, 3SMII, and MII
  • Supports 2K flows, 2K policers, 2K shapers, 2K queues and 256 logical ports, enabling full Ethernet switching between 256 logical ports
  • Full compliance with TR-101, MEF standards including MEF-9 and MEF-14, 802.1ad, 802.1ah, 802.1ag, Y.1731
  • E-LAN, E-Line, including PBB-TE and MPLS-TP together with full PBB, implementing B and I switch in a single device
  • Deterministic 8 Gbps throughput
  • Integrated OAM hardware processor with a hardware packet generator and hardware analyzer

  • Huge parameter search engine data base through a single DDR2, supporting up 128,000 entries including 128,000 MAC address or IP for L2&L3 switching and routing, multicast, classification tables and 32 programmable search tables
  • Hierarchical QoS including WFQ,WRR, WRED and Strict Priority, supporting up to 2K queues
  • 1588v2 clock recovery and 1588 end-to-end transparent clock
  • Synchronous Ethernet
  • MEF-10 compliance policing per stream with 64Kbps granularity and up to 4K streams
  • Advanced hierarchical classification and filtering including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/ Swap/ Extract stamp in any preconfigured location in the first 128 bytes
  • Management is performed through generic CPU interface, MII, GMII or integrated CPU

See Detailed Features

Description

ENET38xx multiservice flow processors and traffic manager solutions are specially developed for Metro Access market. Functionality, throughput,  and standard compliance of ENET38xx are optimized for Carrier Ethernet access, Metro Ethernet demarcation, IP DSLAMs, and ONU for MDU market.

ENET38xx FFPs integrate packet processing, protocol interworking, traffic management and Layer 2/3/4 switch.

Ethernity’s ENET38xx family of multiservice fabric access processors is optimized for Mobile Backhaul transmission networks and Carrier Ethernet Metro markets. Compliant with Metro Ethernet Forum specifications and IETF PWE3, ENET38xx is uniquely positioned to deliver an optimal solution for pseudowire gateways, TDM and Ethernet Access Devices (EAD), Carrier Ethernet Microwave, cellular base stations and broadband access DSL cards, including support for integrated EFM bonding.

The design of ENET38xx is based on a specially efficient architecture resulting in 80%  size reduction, enabling an extremely cost-effective implementation based on low cost FPGAs. Ethernity’s ENET38xx retain the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASICs. ENET38xx are based on atomic level pipeline architecture, and support performance of up to 8Gbps on ultra low cost FPGA, with software configurable L2 to L4 protocol interworking, hierarchical multi field classification and flow identification, virtual Ethernet switch used for VPLS, E-LAN, E-TREE and E-Line, hierarchical policing, performance monitoring, packet editing, hierarchical scheduling and shaping.

Protocol interworking in ENET38xx includes software support for packet editing, which provide ability to receive packets in any format and change a protocol per virtual output port to any other protocol, hence it supports Ethernet II, SNAP, Q-in-Q, MAC-in-MAC, MPLS-TP, PPP, PPPoE , PPPoA ,HDLC, L2TP, AAL5 or any type of L2 protocol.

Detailed Features

Classification
  • Identifies flow and assign several flow IDs per stream, based on 36 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the first 128 bytes of each frame
  • Assigns packet priority based on ingress priority mapping configuration
  • Up to 32K flows filter for any classified packet based on the set of rules and set of the 64 configurable fields
Switching and Routing
  • Fully IEEE 802.1Q compliant Ethernet switch with up to 128K Ethernet MACs, and 16K active network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS, or other packet fields programmed by the software and up to 4K multicast groups
  • Configuration forwarding/switching decision per flow including connection oriented (PBT), PBB, L2, L3 or L4 forwarding decision
  • Full compliance with PBB-TE / PBT and PBB
  • Switching based on inner MAC and combination of network tags
  • 32 software programmable / configurable search tables
  • Configurable forwarding key and learning key per flow
  • Force association of specific MAC to a certain logical port and service
  • 16K L3 address for supporting L3 forwarding
  • Partitioning of MAC address per VPNL2
  • Control packets classifier for both user and network L2 control protocol packets
  • Flexible forward decision per port per protocol with the ability to forward transparently, to CPU or discard
  • Support include ARP, DHCP, IGMPv2, IGMPv3 and other based on flexible configuration options
Quality of Service (QoS)
  • Eight priority queues per virtual port
  • Priority assignment per port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS
  • Configurable L3/L2 priority profiles per port
  • Ingress and egress priority mapping per flow
Policing and Shaping
  • Extended metering according to Three Color scheme as defined by MEF-10 including color aware and coupling flag modes configured per flow
  • Supports up to 4K flows
  • Each ingress and egress flow can be configured in a granularity of 64Kbps up to 100Mbps
Traffic Management
  • Support of  Jumbo frames up to 9.6KB
  • Support of eight priority queues per port / logical port
  • Hierarchical scheduling
  • Programmable values for drop level
  • Two Weighted Fair queuing hierarchies
  • TCP friendly algorithm implemented
Packet Editing
  • Extract, append, or swap in the egress any type of Layer 2/3/4 headers programmed by software, including MAC-in-MAC, Q-In-Q, MPLS, PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP,L3,  or any other header up to 128 bytes, controlled and configured by software
  • L2 and L3 loopbacks including swap of MAC SA and DA, swap of IP.
  • NAT/NAPT
  • Stamp data at the bit/byte level anywhere within the first 128 bytes including priority remapping, bytes count, sequence ID and DSCP.
Traffic Monitoring
  • L2/L3/L4 control packets classifier for both user and network L2 control protocol packets per flow
  • Flexible forward decision per port/flow per protocol with the ability to forward transparently, to CPU or discard
  • OAM packets classifier for both user and network including support for 802.1ag
  • Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or discard
  • Integrate packet generator and analyzer to support generation and analyzing of OAM packets and full support for Y.1731
IGMP Proxy
  • IGMP V2 and V3 compliance
  • IGMP packet snooping to processor in the U/S direction
  • Forwarding and multicast classification based on Source IP and Destination IP
Fragmentation
  • Supports channelized Ethernet according to G.999.1
  • Supports EFM bonding according to 802.1ah
Pseudowire
  • Full support for: SAToP and CESoPSN
  • Adaptive Clock Recovery (1588v2), Common Clock, External Clock and Loopback timing modes
  • Jitter and wander of recovered clocks conform to G.823/G.824, G.8261, jitter buffer – programmable up to 128 msec
  • Option for E3/DS3
  • ATMoPW
Synchronization over Packet
  • 1588 end-to-end Transparent Clock 1588v2
  • Slave mode clock recovery through third part software
  • Synchronous Ethernet
DDR SDRAM Interface
  • External 16-bit DDR2-SDRAM 400 MHz interface
  • Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components
Host CPU Interface
  • Optional Motorola PowerPC 1&2 Glueless interface
  • Up to 66Mhz with 8/16/32 bit bus width
  • MII interface
Configurable Interface Options
  • 8 x SGMII together with 4 x RGMII
  • 4 x 2.5G SGMII
  • 6 x G.999.1 GbE i/f supporting 48 VDSL ports
  • 4 x Utopia/POS II supporting up to 96 ports with dual latency
  • 40 SSSMII
  • SPI-3
  • 32 x E1/T1s – PCM
  • 4/8 x Ch OC-3/STM-1 – SBI
  • Other per customer request