ENET4200 - Radio Access Packet Engine

Overview

ENET4200  access flow processor is a 20Gbps configurable flow processor and traffic manager solution, integrated on Xilinx’s Kintex7 FPGA and optimized for Metro Access market. ENET4200 is tailored to provide the best Carrier Ethernet packet engine for radio access, through support of G.999.1 standard fragmentation, fragment (vs frame) scheduling over radio and header compression, together with EFM bonding to enable best trunking option for several wireless links.


Features

  • 20 Gbps Carrier Ethernet switch integrating flexible interfaces up to 20Gbps including XFI, RXAUI, SGMII, RGMII
  • 20 Gbps fabric flow processor, integrating Carrier Ethernet switch,  MPLS-TP, hierarchical queuing and  scheduling, CFM/OAM through internal OAM processor offload, programmable header compression, G.999.1 and EFM bonding  and protocol interworking, all integrated  on a single  28nm FPGA Xilinx ‘s Kintex7 FPGA
  • Eight 10G integrated SERDES
  • Data interfaces: XFI, QXAUI, QSGMII ( 4 x GbE), SGMII, 6 to 16 x G.999.1 RGMII,  and MII
  • On the fly encapsulation and packet analyzing
  • Classify streams based on five configurable fields with five hierarchies
  • Supports 100ms deep buffering for radio access
  • Channelized Ethernet G.999.1 to support fragmentation and fragment scheduling over radio links or G.vector DSL ports
  • L2/L3/L4 header compression / decompression
  • Supports 16K flows, 16K policers, 16K shapers, 16K queues and 1k virtual ports to enable full Ethernet switching between all 1k virtual ports
  • Full compliance to TR-101, MEF standards including compliance with MEF-9 and MEF-14, 802.1ad, 802.1ah, 802.1ag, Y.1731, E-LAN, E-Line, MPLS-TP, Provide Bridge, and PBB

  • Deterministic 20Gbps throughput
  • Integrated OAM hardware processor with programmable packet generator and analyzer
  • EFM bonding supporting 16 EFM bonding groups, configurable to 2, 4, or 8 ports per group
  • 1588v2 TC/BC/OC and SyncE
  • Huge parameter search engine data base through a single DDR2, supporting up 256,000 entries including 256,000 MAC address or IP for L2 and L3 switching and routing, multicast, classification tables and 32 programmable search tables
  • Hierarchical QoS including WFQ, WRR, WRED and Strict Priority supporting up to 16K queues
  • MEF-10 compliance policing per stream with 64Kbps granularity
  • Advanced hierarchical classification and filtering including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/ Swap/ Extract/ stamp in any preconfigured location in the first 128 bytes
  • Management is performed through generic CPU interface, MII, GMII or integrated CPU

See Detailed Features

Description


Ethernity’s ENET4200 retains the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASIC solutions. The design of ENET4200 is based on an extremely efficient architecture resulting in 80% die size reduction, enabling cost effective implementation based on low cost FPGAs. ENET4200 is based on atomic engines pipeline architecture, and supports performance of up to 20Gbps on ultra low cost FPGA, with software configurable L2 to L4 protocol interworking, hierarchical multi field classification and flow identification, virtual Ethernet switch used for VPLS, E-LAN, E-TREE and E-Line, hierarchical policing, header compression, performance monitoring, packet editing, hierarchical scheduling and shaping.

The protocol interworking in ENET4200 includes software support for packet editing, which provide the ability to receive packets in any format and change a protocol per virtual output port to any other protocol, hence it supports Ethernet II, SNAP, Q-in-Q, PBB, MPLS-TP,GRE, L2TP, and others, programmed by the user.

Detailed Features

Classification
  • Identifies flow and assign several flow IDs per stream, based on 36 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the first 128 bytes of each frame
  • Assigns packet priority based on ingress priority mapping configuration
  • Up to 32K flows filter for any classified packet based on the set of rules and set of the 64 configurable fields
Switching and Routing
  • Fully IEEE 802.1Q compliant Ethernet switch with up to 256K Ethernet MACs, and 16K active network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS or other packet fields programmed by the software and up to 4K multicast groups
  • Configuration forwarding/switching decision per flow including connection oriented, L2, L3 or L4 forwarding decision
  • 32 software programmable / configurable search tables
  • Configurable forwarding key and learning key per flow
  • Force association of specific MAC to a certain logical port and service
  • 16K L3 address for supporting L3 forwarding
  • Partitioning of MAC address per VPNL2
  • Control packets classifier for both user and network L2 control protocol packets
  • Flexible forward decision per port per protocol with the ability to forward transparently, to CPU or discard
  • Support includes ARP, DHCP, IGMPv2, IGMPv3 and other flexible configuration options
Quality of Service (QoS)
  • Hierarchical QoS with 3-5 hierarchies
  • Eight priority queues per virtual port
  • Priority assignment per port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS
  • Configurable L3/L2 priority profiles per port
  • Ingress and egress priority mapping per flow
Policing and Shaping
  • Extended metering according to Three Color scheme as defined by MEF-10 including color aware and coupling flag modes configured per flow
  • Supports up to 16K flows
  • Each ingress and egress flow can be configured in a granularity of 64Kbps up to 100Mbps
Traffic Management
  • Support of Jumbo frames up to 16KB
  • Support of four-eight priority queues per port / logical port
  • Programmable values for drop level
  • Strict priority and dedicated low jitter scheduling
  • Support of eight priority queues per port / virtual port
  • 4 scheduling hierarchies
  • Programmable values for drop level
  • Two Weighted Fair queuing hierarchies
  • TCP friendly algorithm
Packet Editing
  • Extract, append, or swap in the egress any type of Layer 2/3/4 headers programmed by software, including
    Q-In-Q,  PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP,L3,  or any other header up to 128 bytes, controlled and configured by software
  • L2 and L3 loop backs including swap of MAC SA and DA, swap of IP
  • Stamp data at the bit/byte level anywhere within the first 128 bytes including priority remapping, bytes count, sequence ID and DSCP
OAM/CFM
  • Integrated packet generator and analyzer to support OAM packet per MEF 17, Y.1731, and 802.1ag, 802.3 ah including per flow BERT
  • Rate limitation and filtering of OAM messages and other BPDUs to prevent network attacks
  • L2/L3/L4 control packets classifier for both user and network L2 control protocol packets per flow
  • Hardware processing for L2, L3 Loop backs (swap L2 SA/DA, swap L3 SA/DA)
  • Fast protecting switching within micro seconds
  • ELPS G.8031, ERPS G.8032
  • 802.3ah Link OAM
    – Link loopback
    – Unidirectional link fault detection
    – Threshold-based monitoring and notification
  • 802.1ag end-to-end Service OAM and CFM
    – Supports 64 levels of maintenance domains and Maintenance End Points (MEP)
    – Up to 512 Maintenance Associations
    – Connectivity Check Messages (CCM)
    – Remote Defect Indication (RDI)
    – Link trace
    – Diagnostic loopback
  • Integrate packet generator and analyzer to support generation and analyzing of OAM packets and full support for Y.1731
  • Y.1731 performance monitoring
    – Frame delay
    – Frame delay variation (jitter)
    – Frame loss — AIS
EFM bonding & Fragmentation
  • Supports Ethernet fragmentation per G.999.1 to enable prioritization of short packet and jumbo packets over radio links
  • Enable connectivity to G.vector DSL components
  • EFM bonding supporting 16 bonding groups
  • Supports 6 to 16 G.999.1 channelized Ethernet ports
Header Compression
  • Supports L2/L3/L4 header compression / decompression of the first 128 B of the packet
  • End to end automatic learning of original packet type
Synchronization over Packet
  • 1588 end-to-end Transparent Clock 1588v2
  • Slave mode clock recovery through third part software
  • Synchronous Ethernet
L2 Control Protocol
  • L2 control packets classifier for both user and network L2 control protocol packets
  • Flexible forward decision per port/flow per protocol with the ability to forward transparently, to CPU or discard
  • OAM packets classifier for both user and network including support for 802.1ag
  • Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or discard
IGMP Proxy
  • IGMP V2 and V3 compliance
  • IGMP packet snooping to processor in the U/S direction
  • Forwarding and multicast classification based on Source IP and Destination IP
DDR SDRAM Interface
  • External 16-bit DDR2-SDRAM 400 MHz interface
  • Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components
Host CPU Interface
  •  Optional Motorola PowerPC 1&2 Glueless interface
  • Up to 66Mhz with 8/16/32 bit bus width
  • MII interface