ENET48xx 40Gbps Carrier Ethernet switch is a family of high performance configurable flow based processor and traffic manager solutions, optimized for Carrier Ethernet market. ENET48xx Fabric Flow Processor (FFP) is integrated on Xilinx’s Kintex 7 FPGA and provides packet processing, protocol interworking, traffic management, and a Layer 2/3/4 switch. Ethernity’s ENET48xx is uniquely positioned to deliver an optimal solution for Ethernet aggregation, PON OLTs, optical transport ( OTN) mobile backhaul,  and Carrier Ethernet switch and router (CESR).


  • 40 Gbps Carrier Ethernet switch integrating flexible interfaces up to 20Gbps including XFI, RXAUI, SGMII, RGMII
  • 40 Gbps FFP integrating Carrier Ethernet switch,  MPLS-TP, hierarchical queuing and  scheduling, CFM/OAM through internal OAM processor offload,  and protocol interworking, all integrated  on a single 28nm Xilinx ‘s Kintex 7 FPGA
  • Eight/ sixteen 10G integrated SERDES
  • Data interfaces: XFI, QXAUI, QSGMII ( 4 x GbE), SGMII, Interlaken, RGMII,  and MII
  • On the fly encapsulation and packet analyzing
  • Classify streams based on five configurable fields with five hierarchies
  • Supports 64K flows, 64K policers, 64K shapers, 64K queues and 8k virtual ports enable full Ethernet switching between all 8k virtual ports
  • Full compliance to TR-101, MEF standards including compliance with MEF-9 and MEF-14, 802.1ad, 802.1ah, 802.1ag, Y.1731, E-LAN, E-Line, MPLS-TP, PBB, Provider Bridge
  • Deterministic 40Gbps throughput
  • Integrated OAM hardware processor with programmable packet generator and analyzer
  • 1588v2 TC/BC/OC and Sync E
  • Huge parameter search engine data base through a single DDR2, supporting up 256,000 entries including 256,000 MAC address or IP for L2 and L3 switching and routing, multicast, classification tables and 32 programmable search tables
  • Hierarchical QoS including WFQ, WRR, WRED and strict priority supporting up to 64K queues
  • MEF-10 compliance policing per stream with 64Kbps granularity
  • Advanced hierarchical classification and filtering including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/ Swap/ Extract/ stamp in any preconfigured location in the first 128 bytes
  • Interfaces: flexible interface configuration from QSGMII (single 5G SERDES supporting 4 x SGMII), SGMII, RGMII, XFI, RXAUI, and 20G Interlaken
  • Management is performed through generic CPU interface, MII, GMII or integrated CPU


Ethernity’s ENET48xx fabric processor family is optimized for Carrier Ethernet Metro market. Compliant with the latest ITU-T and Metro Ethernet Forum specifications, ENET48xx is uniquely positioned to deliver an optimal solution for Ethernet aggregation, PON OLTs, mobile backhaul, edge and core Carrier Ethernet switch and router (CESR).

The design of ENET48xx FFP is based on an extremely efficient architecture resulting in 80% die size reduction, and enabling an extremely cost effective implementation based on low cost FPGAs. Ethernity’s ENET48xx retain the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASICs.

Protocol interworking in ENET48xx includes software support for packet editing, which provide the ability to receive packets in any format and change a protocol per virtual output port to any other protocol, hence it supports Ethernet II, SNAP, Q-in-Q, PBB, MPLS-TP, GRE, L2TP, and others, programmed by the user.

Detailed Features

  • Identifies flow and assigns several flow IDs per stream, based on 36 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the first 128 bytes of each frame
  • Assigns packet priority based on ingress priority mapping configuration
  • Up to 32K flows filter for any classified packet based on the set of rules and set of the 64 configurable fields
Switching and Routing
  • Fully IEEE 802.1Q compliant Ethernet switch with up to 256K Ethernet MACs, and 16K active network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS or other packet fields programmed by software and up to 4K multicast groups
  • Configuration forwarding/switching decision per flow including connection oriented, L2, L3 or L4 forwarding decision
  • 32 software programmable / configurable search tables
  • Configurable forwarding key and learning key per flow
  • Force association of specific MAC to a certain logical port and service
  • 16K L3 address for supporting L3 forwarding
  • Partitioning of MAC address per VPNL2
  • Control packets classifier for both user and network L2 control protocol packets
  • Flexible forward decision per port per protocol with the ability to forward transparently, to CPU or discard
  • Support include ARP, DHCP, IGMPv2, IGMPv3 and other flexible configuration options
Quality of Service (QoS)
  • Hierarchical QoS with 3-5 hierarchies
  • Eight priority queues per  virtual port
  • Priority assignment per port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS
  • Configurable L3/L2 priority profiles per port
  • Ingress and Egress priority mapping per flow
Policing and Shaping
  • Extended metering according to Three Color scheme as defined by MEF-10 including color aware and coupling flag modes configured per flow
  • Support up to 16K flows
  • Each ingress and egress flow can be configured in a granularity of 64Kbps up to 100Mbps
Traffic Management
  • Support of Jumbo frames up to 16KB
  • Congestion manager: per queue, 8-profile WRED congestion avoidance with 8 programmable profiles
  • Hierarchical MEF-10 metering – on port/service/flow level – any combination of them can be mapped to a specific meter
    – 64K meters, with granularity of 64Kbps
  • Re-marking – based on L3 or L2 information decoded from the packet or set by the service or the flow or the filter
    – Color marking can be done on 3 packet header hierarchies
    – Packet color can be mapped from any header/field decoded from the packet or set by the service/flow/filter
  • Scheduler: hierarchical, three level scheduler per MEF-10
    – Port – WRR  :   Up to 256 ports per interface
    – logical port (cluster) – WFQ, WRR, Strict Priority: up to 8K logical queues
    – Priority queue – WFQ, WRR, Strict Priority : 8 Priority queues per logical port/ queue
  • Queue manager
    – Virtual output queues architecture
    – Total of 64K queues
    – Unlimited MC burst support
    – Configurable buffer size
  • Shaper per queue and each hierarchy – packet, cell or byte level
  • Performance monitoring counters for billing and diagnostics – forward/drop packet and bytes green/yellow/red
  • Configurable MTU per priority queues or per cluster
  • Programmable values for drop level
  • Strict priority and dedicated low jitter scheduling
  • 4 schedluing hierarchies
  • TCP friendly algorithm
Packet Editing
  • Extract, append, or swap in egress any type of Layer 2/3/4 headers programmed by software, including
    Q-In-Q,  PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP, L3,  or any other header up to 128 bytes, controlled and configured by software
  • L2 and L3 loop backs including swap of MAC SA and DA, swap of IP
  • Stamp data at the bit/byte level anywhere within the first 128 bytes including priority remapping, bytes count, sequence ID and DSCP
  • Integrated packet generator and analyzer to support OAM packet per MEF 17, Y.1731, and 802.1ag, 802.3 ah including per flow BERT
  • Rate limitation and filtering of OAM messages and other BPDUs to prevent network attacks
  • L2/L3/L4 control packets classifier for both user and network L2 control protocol packets per flow
  • Hardware processing for L2, L3 loopbacks (swap L2 SA/DA, swap L3 SA/DA)
  • Fast protecting switching within micro seconds
  • ELPS G.8031, ERPS G.8032
  • 802.3ah Link OAM
    – Link loopback
    – Unidirectional link fault detection
    – Threshold-based monitoring and notification
  • 802.1ag end-to-end Service OAM and CFM
    –  Supports 64 levels of maintenance domains and Maintenance End Points (MEP)
    – Up to 512 Maintenance Associations
    – Connectivity Check Messages (CCM)
    – Remote Defect Indication (RDI)
    – Link trace
    – Diagnostic loopback
  • Integrated packet generator and analyzer to provide generation and analyzing of OAM packets and full support for Y.1731
  • Y.1731 performance monitoring
    – Frame delay
    – Frame delay variation (jitter)
    – Frame loss — AIS
Synchronization over Packet
  • 1588 end-to-end Transparent Clock 1588v2
  • Slave mode clock recovery through third part software
  • Synchronous Ethernet
L2 Control Protocol
  • L2 control packets classifier for both user and network L2 control protocol packets
  • Flexible forward decision per port/flow per protocol with the ability to forward transparently, to CPU or discard
  • OAM packets classifier for both user and network including support for 802.1ag
  • Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or discard
IGMP Proxy
  • IGMP V2 and V3 compliance
  • IGMP packet snooping to processor in the U/S direction
  • Forwarding and multicast classification based on Source IP and Destination IP
DDR SDRAM Interface
  • External 16-bit DDR2-SDRAM 400 MHz interface
  • Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components
Host CPU Interface
  •  OptionMotorola PowerPC 1&2 Glueless interface
  • Up to 66Mhz with 8/16/32 bit bus width
  • MII interface