ENET4845Z Evaluation Board

Overview

Ethernity offers an evaluation board to facilitate development, testing, and design based on ENET packet flow processors, minimizing development time and reducing time-to-market.

ENET4845Z EVB is the reference design kit for the ENET48xxZ 40G Carrier Ethernet switch SoC on FPGA. It offers an entire Carrier Ethernet switch and traffic manager integrated on Xilinx’s Zynq 7045 FPGA, with 12 x 1G user ports, 2 x 10G SFP+ interfaces, and 40G of switching capacity.

Features

Packet Processor:

  • Flow-based processor supporting OF/SDN switch
  • L2/3/4 flow classification
  • ACL L2/L3/L4
  • IPSec tunnel with additional VxLAN, NVGRE (special request) overlays
  • Search engine with 256K entries (16 tables)
  • Switch, router, and load balancing functions
  • Five-level packet header & payload manipulation and marking: MPLS/PBB/PB (PBB and MPLS special request)
  • Various types of editing and packet duplication/multicast
  • L2 VPN (special request)
  • LAG (L2, L3, L4 distribution)
  • ERPS, ELPS
  • Y.1731, RFC2544, 802.1ag, OAM, MPLS OAM, BFD, Y.1564
  • Wire speed NAT/NAPT
  • TR101, TR-156, TR-301
  • Header compression/decompression (special request)
  • Hierarchical traffic management
  • Hierarchical scheduling
  • Hierarchical metering
  • Hierarchical shaping

SW SDK:

  • MEA Driver and HAL (HW abstraction layer)
  • MEA CLI
  • Documentation
  • Linux: file system and tool chain

Specifications

  • 12 x 1G (RJ45) interfaces and 2 x 10G interfaces (SFP+)
  • On-board DDR3 operates at 800MHz for packet memory, search and parameters
  • RS232 and GbE port for out-of-band management

Download EVB4845Z Product Brief