Gearing Up for MWCS19 – Q&A About Ethernity’s FPGA SmartNICs
In connection with Mobile World Congress Shanghai 2019, which opens this Wednesday, we did a question-and-answer session for two Chinese publications. The subject was FPGA SmartNICs, and we thought that it might be instructive to see the questions asked for the article and how we responded.
Question 1: Ethernity’s flagship products are SmartNICs. Why use a SmartNIC at all?
SmartNICs – programmable network interface cards – are used in servers for offloading networking and security data plane functions from the CPU, in cloud infrastructure, data centers, and, more recently, at the network edge. As telco/cloud service providers and enterprise IT deployments move from traditional ASIC-based network equipment to x86 architecture-based networking and COTS servers, a once rigid network of dedicated fixed-function devices is gradually transforming into a flexible network of standard servers and programmable network appliances.
This transformation aims to reduce costs and vendor lock-in, and provides the ability to change or implement new functionality as quickly as the market requires, within weeks instead of years.
However, processing networking data overburdens the server CPU, and multiple (or sometimes all) CPU cores are required to process common networking functions even at 10 Gbps of data traffic. At rates above 40 Gbps throughput, CPU performance suffers from high variability and unpredictability in throughput and latency.
Adding more CPUs and servers is not cost-effective and still suffers in performance. With SmartNICs, the data plane and control plane are separated, and the data plane can scale economically, simply by adding SmartNICs whenever there is a need for additional bandwidth.
At Ethernity, we believe that you can stop burning CPU cores on networking tasks by offloading them to a SmartNIC, which can perform them more effectively. Offloading reduces costs and provides deterministic increased performance for functions such as vBRAS and vBNG, vEPC, IPSec gateway, and network gateway.
Question 2: What are the benefits of FPGA-based SmartNICs?
An FPGA can be reprogrammed as needed, instead of replacing the whole card, if the application or use case changes. FPGA SmartNICs are also especially effective in reducing latency, increasing throughput, and reducing power consumption.
Deterministic low latency is a great advantage. By using an FPGA, it is feasible to achieve a latency around or below one microsecond (ms), because FPGAs don’t rely on the operating system. By comparison, when a CPU is used for networking, a latency smaller than 50 ms is considered very good.
With an FPGA, a network interface connects directly to the pins of the chip, which therefore offers very high bandwidth (as well as low latency) and better ability to scale for high throughput applications. That’s why FPGA SmartNICs are indispensable in next-generation networks.
Power efficiency is just as important. FPGAs intrinsically handle the logic computations used for acceleration with little energy output. Also, FPGA SmartNICs do not require a host CPU to handle the networking, saving additional energy on the host side.
For example, we compared virtual Broadband Network Gateway (vBNG) performance and cost in a side-by-side test between a server-only setup and one using FPGA SmartNIC acceleration. In every test, FPGA SmartNICs demonstrated superior efficiency. Core utilization, for example, never exceeded eight percent even at 200 Gbps total throughput.
In power consumption, FPGA SmartNIC usage was one-tenth that of a server-only approach at 200 Gbps, and never exceeded 26 percent at any data rate. And in the cost comparison, the FPGA SmartNIC approach cost a small fraction of the server-only method at all data rates.
Another important advantage of SmartNICs is in cybersecurity by isolating the networking from the compute. Should the CPU be hacked, the data path (handled by the FPGA) is still protected. The FPGA also can handle security functions such as encryption, ACL, and firewall, thereby protecting the CPU from malicious attacks.
Question 3: Among FPGA SmartNICs, what specific advantages do Ethernity’s ACE-NICs offer?
In addition to all the aforementioned advantages of FPGA SmartNICs, Ethernity’s ACE-NICs contain patented technology to use fewer internal logical and memory elements than other SmartNICs. We also have our own method to work with external memory. This allows us to use the smallest 16nm FPGAs, saving both cost and die size for our customers.
Ethernity’s ENET Technology includes a full switch-router on a SmartNIC. While others can handle specific tasks, no one else offers a complete router-on-a-NIC. Our software stack has a complete suite of layer 2 and 3 network control protocols for Carrier Ethernet, performance monitoring, security, MPLS, timing synchronization, H-QoS, IPv4/v6, tunneling, and many more networking features.
Moreover, ENET Technology includes an SDK with hardware adaptation layer (HAL), Metro Ethernet Adaptor CLI, FPGA drivers and user space APIs, enabling fast solution development and quick time-to-market for our OEM customers.
Question 4: What new products are you bringing to MWC this year?
Ethernity provides a range of turnkey solutions including SoCs, SmartNICs, and network appliances, all built around the rich capabilities of the ENET Flow Processor. This year, our newest addition is the ENET Universal Edge Platform (UEP).
The ENET UEP is a modular and programmable network appliance offering a network-edge-optimized, low-space/low-power FPGA-based device with up to 40Gbps of networking capacity and 10Gbps of IPSec security performance with flexible interface and port configurations.
The UEP’s unique modularity enables the appliance to be easy adapted for multiple edge use cases, such as a network interface device (NID), distribution point unit (DPU) and multi-dwelling unit (MDU), and 5G cell site router (CSR). The additional flexibility provided by the PCIe connection to a standard server allows it to act as viable accelerator to NFV workloads at the network edge.
The product uses standard DPDK to fully offload up to 80Gbps of data processing to the ACE-NIC100’s onboard FPGA, minimizing CPU intervention, saving CPU cycles, and significantly reducing CPU power and cost. Moreover, the ACE-NIC100 will support tens of thousands of subscribers with PPPoE termination, performance monitoring counters per subscriber, and H-QoS, which is impractical for implementation in software-only BNG.
With FiberHome’s powerful software and Ethernity’s FPGA-based hardware, the product will provide high performance and reduced cost through hardware acceleration, making it especially attractive to Chinese service providers.