ENET3850Z Switch-Router Flow Processor

Overview

ENET3850Z is a 6Gbps configurable flow processor, implemented on Xilinx‘s Zynq FPGA, integrating packet processing, protocol interworking, hierarchical traffic management, MPLS-TP, and a Layer 2/3/4 switch aimed at the Metro Access Market. ENET3850Z is specially optimized for Carrier Ethernet Access, Avionics, and Metro Ethernet demarcation (NID).
The design of ENET3850Z is based on an especially efficient architecture resulting in 80% size reduction, enabling an extremely cost-effective implementation based on low cost FPGAs. Ethernity’s ENET3850Z retains the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASICs.

Features

  • 6Gbps fabric flow processor supporting Carrier Ethernet switch, hierarchical queuing and scheduling, and protocol interworking, all integrated on a single 40nm FPGA
  • Supports 4K flows, 256 policers, 256 shapers, 256 queues, and 32 logical ports, enabling full Ethernet switching
  • Full compliance with TR-101, MEF standards including MEF-9 and MEF-14
  • Deterministic 6Gbps throughput
  • Huge parameter search engine database through a single DDR, supporting up to 64K entries including MAC addresses and IP for L2&L3 switching and routing, multicast, classification tables, and 32 programmable search tables
  • ACL L2/L3/L4
  • Hierarchical QoS including WFQ, WRR, WRED, and Strict Priority
  • Advanced hierarchical classification and filtering, including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/Swap/Extract/Stamp in any preconfigured location in the first 128 bytes
  • Management is performed through a generic CPU interface, MII or integrated CPU

Specifications

  • External 16-bit DDR 800MHz interface
  • Configurable interface options:
    -4 x SGMII together with 4 x RGMII
    -4 x 2.5G SGMII
    -QSGMII
    -Other up to 6Gbps