ENET4840Z Switch-Router Flow Processor

Overview

The ENET4840Z 20-40Gbps Carrier Ethernet switch is a high performance configurable flow-based processor and traffic manager, optimized for the Carrier Ethernet market. The ENET4840Z Flow Processor is integrated on a Xilinx FPGA and provides packet processing, protocol interworking, traffic management, and a Layer 2/3/4 switch, and as such, is uniquely positioned to deliver an optimal solution for Ethernet aggregation, PON OLTs, optical transport (OTN) mobile backhaul, and Carrier Ethernet switch and router (CESR).

Features

  • 20/40Gbps Flow Processor supporting Carrier Ethernet switch-router, MPLS-TP, hierarchical queuing and scheduling, CFM/OAM through internal OAM processor offload, protocol interworking, and multiple tunneling options, all integrated on a single 28nm Xilinx FPGA
  • 8/16 x 10G integrated SeRDeS
  • On-the-fly encapsulation and packet analyzing
  • Classifies streams based on five configurable fields with five hierarchies
  • Supports 256K flows, 256K policers, 64K shapers, 64K queues, and 2K virtual ports, enabling full Ethernet switching between all virtual ports
  • Full compliance with TR-101, MEF standards including compliance with MEF-9 and MEF-14, E-LAN, E-Line, MPLS-TP, PBB, and Provider Bridging
  • Integrated OAM hardware processor with 802.1ad, 802.1ah, 802.1ag, and Y.1731,
    1588v2 TC/BC/OC and SyncE
  • Search engine database through a single DDR, supporting up to 256,000 entries, including 256,000 MAC addresses and IP for L2 and L3 switching and routing, multicast, classification tables, and 32 programmable search tables
  • NAT/NAPT
  • Various overlay methods: VxLAN, NVGRE, L2TP
  • Complete support for 3GPP tunnel for mobile solutions
  • Ethernet and IP fragmentation
  • Header compression
  • ACL L2/L3/L4
  • Hierarchical QoS, including WFQ, WRR, WRED, and Strict Priority, supporting up to 64K queues
  • MEF-10 compliance policing per stream with 64Kbps granularity
  • Advanced hierarchical classification and filtering, including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/Swap/Extract/Stamp in any preconfigured location in the first 128 bytes
  • Management is performed through a generic CPU interface or integrated CPU
  • Optional IPSec Tunnel available per project

Specifications

  • 8/16 x SGMII/QSGMII/10BASE-R SERDES
  • Additional RGMII interfaces
  • DDR3 x 6 (search, descriptors, and buffer) 800MHz