ENET5100Z Switch-Router Flow Processor

Overview

The ENET5100Z 50-100Gbps Carrier Ethernet switch is a high performance configurable flow-based processor and traffic manager, optimized for the Carrier Ethernet market. The ENET51000Z Flow Processor is integrated on Xilinx’s Utrascale FPGA and provides packet processing, protocol interworking, traffic management, and a Layer 2/3/4 switch, and as such, is uniquely positioned to deliver an optimal solution for Ethernet aggregation, PON OLTs, mobile backhaul, and Carrier Ethernet switch and router (CESR).

Features

  • 50 to 100Gbps Carrier Ethernet switch integrating flexible 1/10/25/40G interfaces, MPLS-TP, hierarchical queuing and scheduling, CFM/OAM through internal OAM processor offload, and protocol interworking, all integrated on a single 16nm Xilinx FPGA
  • On-the-fly encapsulation and packet analyzing
  • External buffering
  • Classifies streams based on five configurable fields with four hierarchies
  • Supports 4M flows, 512K policers, 256K shapers, 256K queues, and 8K virtual ports, enabling full Ethernet switching between all 8K virtual ports
  • Full compliance with TR-101, MEF standards including compliance with MEF-9 and MEF-14, E-LAN, E-Line, MPLS-TP, PBB, and Provider Bridging
  • Various overlay methods: VxLAN, NVGRE, L2TP
  • Complete support for 3GPP tunnel for mobile solutions
  • Integrated OAM hardware processor with programmable packet generator for 802.1ad, 802.1ah, 802.1ag, and Y.1731
  • 1588v2 TC/BC/OC and SyncE
  • Search engine database through a single DDR4, supporting up to 4M entries including MAC addresses and IP for L2 and L3 switching and routing, multicast, classification tables, and 32 programmable search tables
  • Enhanced ACL engine with 9 tuples
  • Hierarchical QoS including WFQ, WRR, WRED, and Strict Priority, supporting up to 256K queues
  • MEF-10 compliance policing per stream with 64Kbps granularity
  • Advanced hierarchical classification and filtering, including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per-flow multiple actions of Append/Swap/Extract/Stamp in any preconfigured location in the first 128 bytes
  • Management is performed through a generic CPU interface (dual-core ARM v8)
  • Optional IPSec Tunnel available per project

Specifications

  • Flexible interface configuration: QSGMII, SGMII, RGMII, KR, KR4, CGMII, and 150G Interlake
  • 10 x DDR4 (2660MHz)