ENET4200Z Switch-Router Flow Processor


ENET42000Z is a 16Gbps configurable flow processor, implemented on a Xilinx Zynq FPGA, integrating packet processing, protocol interworking, hierarchical traffic management, CFM/OAM, and a Layer 2/3/4 switch aimed at the Metro Access Market.
The ENET4200Z is a Metro Ethernet Forum-compliant multiservice flow processor and traffic manager that is uniquely positioned to deliver an optimal solution for Carrier Ethernet providers.


  • 16Gbps flow processor supporting Carrier Ethernet switch, hierarchical queuing and scheduling, CFM/OAM through internal OAM processor offload, and protocol interworking, all integrated on a single 40nm FPGA
  • Supports 2K flows, 1K policers, 1K shapers, 1K queues, and 256 logical ports, enabling full Ethernet switching
  • Full compliance with TR-101, MEF standards including MEF-9 and MEF-14
  • E-LAN, E-Line, and PBB models are supported
  • Integrated OAM hardware processor with a hardware packet generator and hardware analyzer, supporting 802.1ad, 802.1ah, 802.1ag, and Y.1731
  • Search engine database through a single DDR, supporting up to 256K entries, including MAC addresses and IP for L2&L3 switching and routing, multicast, classification tables, and 32 programmable search tables
  • ACL L2/L3/L4
  • 2K Multicast entries
  • Hierarchical QoS including WFQ, WRR, WRED, and Strict Priority
  • VxLAN, NVGRE, L2TP, IPinIP tunnels
  • MEF-10 compliance policing per stream with 64Kbps granularity and up to 4K streams
  • Advanced hierarchical classification and filtering, including configurable packet parsing and configurable search keys
  • Programmable packet editor supporting per flow multiple actions of Append/Swap/Extract/Stamp in any preconfigured location in the first 128 bytes
  • IP fragmentation and header compression for radio networks
  • Management is performed through a generic CPU interface or integrated CPU


  • 4 x 1/2.5/5/10G SGMII/ QSGMII/10BASE-R network interfaces
  • External 2 x 16-bit DDR 800MHz interface